1. Field of Invention
The present invention relates to low power RAM and in particular the speed by which low power RAM is powered up and switched between standby and active states.
2. Description of Related Art
The popularity of portable devices has created a need for low power devices and in particular low power RAM, which can conserve power and at the same time provide a quick response to the request for data. Low power techniques are one of the keys to the advancement of portable devices. In low power memory devices the power-up procedure can be relatively slow, which is caused in part by waiting for the internal power circuits to be charged. To assist in charging the internal power circuitry, dummy cycles are used to permit time to charge the power circuits.
In the low power applications, the power consumption of a memory device (RAM) in an active mode versus a standby mode is divergent. In some low power RAM chips the power consumption in the active mode is two to three orders of magnitude larger than in standby mode. The internal power of a low power RAM is created with on-chip voltage generators, which consist of large and small voltage converters. The large voltage converters have a high capacity for supplying the required internal chip power, and also consume additional power in their operation. Both the large and small converters are turned on when the RAM chips operate in an active mode, i.e. read, write and auto refresh. In self refresh mode and standby mode only the small converters are used in low power RAM.
U.S. Pat. No. 5,617,062 (O'Shaughnessy) describes a timer initialization circuit, which has a rapid initialization on power-up. The circuit is used to stabilize a timing signal of a timed system using a core oscillator. The initialization circuit disables the core oscillator in a power down and re-enables the oscillator upon termination of the power down mode. In U.S. Pat. No. 5,640,083 (Alexis) a method and apparatus are described for improving the power up time of flash EEPROM memory arrays. The apparatus includes a circuit with a rapidly rise of the value of voltage at a circuit node, which includes connecting one of the charging circuits to a circuit node for a first limited period and then connecting another of the charging circuits to the circuit node thereafter. U.S. Pat. No. 6,667,642 (Moyal) discloses a method and circuit for reducing the power up time of a phase lock loop (PLL). In one embodiment, the invention cuts off a first voltage to the phase lock loop, thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of a filter node within the phase lock loop while the other components of the phase lock loop are powered down.
In FIG. 1A is shown a block diagram of prior art for the voltage generation within a low power memory chip when a standby signal SBY is off, and the memory chip is in an active state. Both the large capacity voltage converters LCVC and the small capacity voltage converters SCVC are in the on state. The converters are supplied with VDD, the memory chip power supply voltage, and VSS, the memory chip ground voltage. In the active state normal chip operations, such as read, write and refresh, are performed and require the large capacity voltage converters LCVC to be in the on state to supply the necessary energy to allow the memory chip to meet its specifications. The LCVC and SCVC converters produce various internal memory chip voltages, which include VCC the memory peripheral circuit power supply, VCCSA the sense amplifier power supply voltage, VBL the bit line voltage, VPL the memory cell plate voltage, VPP the word line voltage and VBB the memory substrate voltage.
In FIG. 1B is shown a block diagram of prior art for the voltage generation within a low power memory chip when a standby signal SBY is on, and the memory chip is in a standby state. The large capacity voltage converters LCVC are turned off in the standby state to conserve power, and the small capacity voltage converters SCVC are left on to be able to maintain charge on the various internal voltage lines.
In FIG. 2 is shown a voltage diagram of prior art, which reflects the operation of the voltage converters shown in FIGS. 1A and 1B. Starting in Phase I, the low powered memory chip is turned on with powering on of VDD. The standby signal is also on and comes up to full strength along with VDD by the end of Phase I. At the same time the “power-up” PU voltage is off as is the LCVC and the SCVC converters are on in Phase I. After the external memory chip voltage VDD has reached full value, Phase II, a standby phase, is started. Phase II is approximately 200 us long and is used to allow the various internal voltage to stabilize. During Phase II the system cannot issue any active memory commands since the various internal voltages are not ready and the LCVC converter is off while the SCVC converter remains on.
Continuing to refer to FIG. 2, In Phase III there are at least two dummy active commands issued to help charge the internal power lines. Phase III is approximately twice trcmin in length, where trcmin=minimum active cycle time, and the power up signal PU is activated within Phase III. Both the LCVC and the SCVC converters are on in Phase III. In Phase IV, an active phase, the standby SBY signal off and a power-up PU signal on. Both the LCVC and the SCVC converters are on and the memory chip is ready to perform normal memory operations, such as read, write and cell refresh. At the end of Phase IV the standby signal SBY is raise an the memory chip enters a standby Phase V. In Phase V the LCVC converters are off and the SCVC converters remain on supplying charge to the various internal power lines within the memory chip.
The continued demand for speed up of the operation of low power RAM memory devices necessitates finding ways to produce a low power device, which meets a stringent set of specifications, and to also provide a quick response from the low powered device used in portable applications. Improving the power-up procedure for low power RAM promotes development of portable devices containing low powered RAM.